1. Field of the Invention
The present invention relates to a pressure contact type semiconductor device typified by a self-commutating thyristor such as a gate turn-off (GTO) thyristor or a gate commutated turn-off (GCT) thyristor, for example. More particularly, according to the present invention, a semiconductor substrate of the device includes at least one outermost segment and/or at least one innermost segment each functioning as a dummy segment. The present invention is applicable to a power device such as a BTB or SVG, for example. For industrial purposes, the present invention is applicable to an inverter for driving a steelmaking rolling machine. Further, the present invention is also applicable to a high voltage/large capacitance switch or the like.
2. Description of the Background Art
A basic structure of a GTO thyristor as one example of a pressure contact type semiconductor device is described in Japanese Patent Application Laid-Open Nos. 62-7163, 61-5533 and 63-318161, for example. According to Japanese Patent Application Laid-Open No. 62-7163, a silicon wafer serving as a semiconductor substrate of a GTO thyristor has a four-layer structure of a p-emitter layer, an n-base layer, a p-base layer and an n-emitter layer. The n-emitter layer is the uppermost layer and is formed of a number of segments each having an island-like protruding portion which are surrounded by the p-base layer.
A basic structure of a GCT thyristor is described in Japanese Patent No. 3191653 (hereinafter referred to as “JP 3191653”), for example. As described in this reference, a structure of a silicon wafer serving as a semiconductor substrate of a GCT thyristor is substantially identical to that of a GTO thyristor.
FIG. 9 is a view showing a profile of step heights of protruding portions of segments, which is obtained as a result of measurement on a semiconductor substrate of a pressure contact type semiconductor device having a conventional structure in an x-axis direction and a y-axis direction (it is noted that FIG. 9 is not admitted as prior art of the present invention). As shown in FIG. 9, the step heights vary such that: a step height at an inner side face of a protruding portion of each innermost segment is the smallest; a step height at a side face of each segment outer than each innermost segment is kept relatively large; and a step height at an outer side face of a protruding portion of each outermost segment is as small as that at the inner side face of each innermost segment. The inventors of the present invention suppose that the following factors are responsible for the foregoing variation in step height.
A typical method of forming a stepped structure on a main surface of a semiconductor substrate is wet etching employing a liquid mixture of a hydrofluoric acid or a nitric acid. In this regard, to perform wet etching on a silicon wafer with the whole of the silicon wafer being immersed in a liquid mixture would result in reduction of an etching rate, so that difference in concentration of the liquid mixture in a surface of the silicon wafer can responsively affect a step height to be created. Thus, uniformity in step height cannot be achieved. In view of this, it is necessary to increase an etching rate in order to perform etching so as to achieve uniformity in step height in accordance with a cathode segment pattern. In one attempt, a portion of a silicon wafer which is rotating is drawn out of a surface of a liquid mixture and is kept exposed to an oxygen atmosphere, thereby to involve oxygen in the form of a bubble into the liquid mixture, during etching. This accelerates reaction, to increase an etching rate.
However, a main surface of a semiconductor substrate generally includes an area reserved for formation of a pattern for extracting a gate electrode (gate electrode extraction pattern) for establishing contact between a gate electrode pattern in each segment and an external gate electrode. This area is located inner than each innermost segment or outer than each outermost segment and should be flat. For this reason, it is impossible to continuously hold bubbles 25 between segments to be sequentially etched, as demonstrated by FIG. 10 which schematically illustrates a state where etching is being carried out on a semiconductor substrate of a center gate type device (it is noted that FIG. 10 is not admitted as prior art of the present invent). As is illustrated in FIG. 10, each of the bubbles 25 which is involved in the vicinity of the flat area can not stop and is flown toward outer segments. As a result, an etching rate for each innermost segment is reduced.
FIG. 11 is a longitudinal sectional view of a semiconductor substrate which is manufactured in such a manner that an etching rate for innermost and outermost segments is reduced as compared to that for the other segments (it is noted that FIG. 11 is not admitted as prior art of the present invention). A portion surrounded by a circle “B” in FIG. 11 shows a structure of one innermost segment. FIG. 12 is an enlarged plan view of a protruding portion of the innermost segment in the portion “B” of FIG. 11, and FIG. 13 is an enlarged longitudinal sectional view of the innermost segment in the portion “B” of FIG. 11 (it is noted that FIGS. 12 and 13 are not admitted as prior art of the present invention). A portion surrounded by a circle “C” in FIG. 11 shows a structure of one outermost segment. As shown in FIGS. 11, 12 and 13, there is a gap in step height between opposite side faces of the protruding portion of the innermost segment, one of which side faces is located closer to a gate electrode extraction pattern, and between opposite side faces of a protruding portion of the outermost segment, one of which side faces is located closer to another gate electrode extraction pattern. It should be noted that in the structures shown in FIGS. 11, 12 and 13, a PN junction is not exposed in the side face of the protruding portion of each of the innermost segment and the outermost segment, which side face is located closer to the gate electrode pattern. Accordingly, an N-type emitter layer NE of the innermost or outermost segment on which a cathode electrode is to be formed extends to be located immediately under a pattern of a gate electrode 1G-AL which should be in contact with an external gate electrode 8. Such a situation is illustrated in a portion surrounded by a circle “D” in FIG. 13. Consequently, in a device having a gap in step height as described above, a cathode electrode and a gate electrode are short-circuited to each other.
Alternatively, depending on a degree of non-uniformity in etching for creating a step height, a stepped structure with a gap in step height as shown in FIG. 14 (it is noted that FIG. 14 is not admitted as prior art of the present invention) may be formed. In the structure shown in FIG. 14, a PN junction is located in the vicinity of a “valley” created between two adjacent protruding portions, which results in reduction of a breakdown voltage between a cathode electrode and a gate electrode.
One possible solution to the foregoing problems is to define a larger step height than a typical step height in etching for creating a step height. However, though this solution avoids reduction of a breakdown voltage or formation of a short circuit between a cathode electrode and a gate electrode, it produces another problem. Specifically, a step height created by each of protruding portions of the other segments than innermost and outermost segments is too large, so that it is very likely that a thickness of a P-type base layer PB is locally reduced. Such local reduction in thickness of the P-type base layer PB, if occurs, would significantly affect electrical characteristics, to degrade an operational performance of a GTO thyristor. Therefore, the foregoing solution is not entirely satisfactory.
Under the above-described circumstances, when a defective semiconductor substrate such as a substrate having the structure as shown in FIG. 11, 12, 13 or 14 is manufactured, to reject the defective semiconductor substrate, not employing it as a product, is one safe countermeasure for avoiding the foregoing problems. However, this countermeasure would suffer from decrease in yield due to rejection of defective semiconductor substrates in a process of quality inspection during manufacture.